Successive approximation register (SAR) analog-to-digital converters (ADCs) may achieve high resolution but are limited in the speed they can achieve. Two components that limit the speed of asynchronous successive approximation register analog-to-digital converters are (1) the settling time of a digital-to-analog converter (DAC) that is utilized by the ADC, and (2) the metastability of the comparator that is utilized by the ADC.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.